Description

The Infra-Silicon team at Meta designs and develops custom Application-Specific Integrated Circuits (ASICs) that power Meta's data center infrastructure. These domain-specific chips are purpose-built to accelerate computationally intensive workloads, including AI inference, video processing, and networking at scale. In this role, you will contribute to the full front-end design lifecycle of next-generation silicon, from microarchitecture definition through RTL implementation and handoff to physical design teams, working closely with architecture, verification, and implementation engineers to deliver high-performance, power-efficient silicon solutions.

ASIC Engineer, Design Responsibilities:

• Develop and refine micro-architecture specifications for complex digital logic blocks including control paths, data paths, and interconnects
• Implement RTL designs in Verilog or SystemVerilog based on micro-architecture specifications and design requirements
• Collaborate with verification engineers to review test plans, coverage results, and debug functional failures at the block and chip level
• Partner with physical design and implementation teams to resolve timing, area, and power closure issues through RTL and constraint refinement
• Identify, evaluate, and integrate soft and hard IP components into the SoC design flow
• Participate in design reviews and contribute to micro-architecture documentation and specification updates
• Support emulation and prototyping efforts to enable early software bring-up and system-level validation
• Analyze power consumption and contribute to low-power design techniques such as clock gating and power domain partitioning
• Collaborate with architecture teams to translate algorithmic requirements into implementable hardware micro-architectures

Minimum Qualifications:

• Bachelor's degree in Electronics and Communication, Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
• 2+ years of experience in digital ASIC or SoC front-end design
• Experience in one of these skills: Micro-architecture and RTL development for complex control/data path and networking IPs (Intellectual Properties), OR Experience in SoC (System on Chip) Micro-architecture, Design and Integration, OR Implementation, Power methodology development
• Experience with RTL coding using Verilog or SystemVerilog

Preferred Qualifications:

• Experience with lint, CDC, RDC analysis and flows
• Knowledge and hands-on experience with AMBA-AXI, PCIe or networking protocols
• Experience with synthesis, static timing analysis, and timing closure methodologies
• Experience collaborating with verification or physical design teams during the silicon development cycle
• Experience designing data path or memory subsystem logic for AI, networking, or video processing workloads

About Meta:

Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today-beyond the constraints of screens, the limits of distance, and even the rules of physics.

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.